Design Engineer

You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency. You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions. As a Hardware Design Engineer, you will: Work closely with senior members of the hardware team to understand requirements and hardware architectures to translate them into mirco-architectures for RTL implementations Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches Support verification of your implementation and fix any issues found. Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA Essential: Knowledge of an RTL language (Verilog, SystemVerilog, VHDL) for complex ASIC/FPGA products A strong skillset in delivering digital designs in the ASIC or FPGA industry Track record in collaborating across teams to produce integrated solutions Experience in technical documentation writing – design specifications, user guides, verification plans Experienced user of EDA tools for simulation and synthesis Desirable: Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Familiarity with the AMBA bus protocols Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience using C++/SystemC for design modelling and integration Experience with high speed interfaces such as PCI-E or JESD Knowledge of a scripting language, such as Python Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools